Cypress Semiconductor

Description

Jul 21, 2016 C1__DWG_PN_3_0. JAE TERMINAL. C1__DWG_PN_4_0. 286692-1. C1__ DWG_PN_1_1. IL - AG5 - C1 - 5000 . C1__DWG_PN_2_1. 286692-2. include information about DSP audio, video, and communications systems for the C5000 and. C6000 DSP CI Link 1 Configuration Register. 02BD 8804 0x4A1A_5000 . 0x4A1A_5FFF DVDD_DDR[1]. DDR[1] Data Bus. IPD. DDR[1 ]_D[7]. C1 . I/O. DVDD_DDR[1]. IPD. DDR[1]_D[6] UART0 Transmit Data Output. Functions as CIR transmit. UART0_TXD. AG5 . O. PINCNTL71 IL . OL. V. = V MIN (or V. MIN) ref. IH. OH. Vref. Transmission Line. 4.0 pF. 1.85 pF. Z0 = 50. Jun 5, 2004 Processor. C1 . Halt. Passive Cooling. Passive Cooling is supported by Stop Grant (throttling). AG5 . L1_CADOUT_L[7] /. NC_A12. 1. A12. L1_CLKOUT_L[ 1] / Il . Input Leakage Current. mA. 1. 1. IOZ. Output Tristate Leakage Current L*_CLKOUT_H/L[1:0]. pS. 0. 5000 . TSU. Device Setup Time. pS. AG5 . I. IPD. EMAC0 configuration select pin (for details, see Table 3-1). . C1 . BED07. E5. BED06. D3. BED05. B2. BED04. C3. BED03. D5. BED02. B3 information about DSP audio, video, and communications systems for the C5000 and ref. IL . OL. TMS320C6472. SPRS612G JUNE 2009 REVISED JULY 2011.